DRAM size independence in single-core processors using gem5

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Published: Jul 7, 2016
Keywords:
cache, dram, gem5, memory hierarchy-, parsec

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Andrés Gallego-Garcés
Facultad de Ingeniería, Grupo de Microelectrónica (GMUN), Universidad Nacional de Colombia
Sebastián Eslava-Garzón
Facultad de Ingeniería, Grupo de Microelectrónica (GMUN), Universidad Nacional de Colombia

Abstract

Energy consumption, speed of execution, and integrated circuit area have become important topics in recent years thanks to the growth of the market for mobile devices and the manufacturers of these devices who try to push the limits of their products while maintaining an affordable price. In that race, the constant evaluation of the hierarchy of memory is now a necessary step if we want to improve execution and utilization of devices’ resources, because this not only affects the consumption of energy, but also the system capacity and price, known as the bottleneck for instruction execution because each task carried out by the processor must be brought from memory first and later return through it. This document shows how the size of the DRAM does not have a significant effect related to execution benchmarks such as PARSEC 3.0, running on an ARM machine (which in this case is an ARM Cortex-A8). The environment for this simulation is gem5, which is an open source platform for various architectures and is able to change the size of the memory. It is precisely this ability and the ARMv7 architecture model that allows the performance to be related to the memory hierarchy and all other aspects to remain the same within the emulated processor throughout the entire process.

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How to Cite
Gallego-Garcés, A., & Eslava-Garzón, S. (2016). DRAM size independence in single-core processors using gem5. Ingenio Magno, 6(2), 40-47. Retrieved from http://revistas.ustatunja.edu.co/index.php/ingeniomagno/article/view/1091
Issue
Vol. 6 (2015): Ingenio Magno Vol. 6-2
Section
Artículos Vol. 6-2

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