DRAM size independence in single-core processors using gem5

Contenido principal del artículo

Andrés Gallego-Garcés
Sebastián Eslava-Garzón


Energy consumption, speed of execution, and integrated circuit area have become important topics in recent years thanks to the growth of the market for mobile devices and the manufacturers of these devices who try to push the limits of their products while maintaining an affordable price. In that race, the constant evaluation of the hierarchy of memory is now a necessary step if we want to improve execution and utilization of devices’ resources, because this not only affects the consumption of energy, but also the system capacity and price, known as the bottleneck for instruction execution because each task carried out by the processor must be brought from memory first and later return through it. This document shows how the size of the DRAM does not have a significant effect related to execution benchmarks such as PARSEC 3.0, running on an ARM machine (which in this case is an ARM Cortex-A8). The environment for this simulation is gem5, which is an open source platform for various architectures and is able to change the size of the memory. It is precisely this ability and the ARMv7 architecture model that allows the performance to be related to the memory hierarchy and all other aspects to remain the same within the emulated processor throughout the entire process.


La descarga de datos todavía no está disponible.

Detalles del artículo

Cómo citar
Gallego-Garcés, A., & Eslava-Garzón, S. (2016). DRAM size independence in single-core processors using gem5. Ingenio Magno, 6(2), 40-47. Recuperado a partir de http://revistas.ustatunja.edu.co/index.php/ingeniomagno/article/view/1091
Artículos Vol. 6-2


Ltd. ARM (2009). Amba LPDDR2 dynamic memory controller DMC-342 technical reference manual. Tech. Rep.Retrieved from http://infocenter.arm.com/help/index. jsp?topic=/com.arm.doc.ddi0436a/index.html
ARM (2013). Cortex A8 Technical Reference Manual. Revision: R2p1. http://infocenter.arm.com/help/index. jsp?topic=/com.arm.doc.ddi0344i/index.html (2013).
C. Augustine, C., X. Mojumder, X, H. Fong, H, S. Choday, S., P. Park, P. and & K. Roy, K. (2012). STT-MRAMs for future universal memories: perspective and prospective. Proc. of 2012 28th Int. Conf. on Microelectronics, 349355.
Inc. Cadence Design Systems (2013a). Cadence design ip: Wide-i/o controller. Tech. Rep.
Inc. Cadence Design Systems (2013b). Sources of error in full-system simulation. Advanced Computer Architecture Laboratory, Michigan: University of Michigan, Advanced Computer Architecture Laboratory..
Fernando Endo, F., Damien Couroussé, D. & and Charles, H.P.. Henri-Pierre (2014). Microarchitectural simulation of in-order and out-of-order arm microprocessors with gem5. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).
Xuanyao Fong, X. and& Kaushik Roy, K. (2013). Lowpower robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches. West Lafayette: Purdue University.
Hansson, A., Agarwal, N., Kolli, A., Wenisch, T. & and Udipi, A. (2014). Simulating dram controllers for future system architecture exploration. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS).
David Money Harris, D. and& Sarah L. Harris, S. (2007).. Digital Design and Computer Architecture. California: Elsevier., inc.1, 2007.
John Hennessy, H. and& David. Patterson, D. . Computer Organization and Design (2009). The hardware software interface (4th ed.). California. Elsevier inc.
Hennessy, H. & Patterson, D. (2012). Computer architecture: a quantitative approach (2012). (5th ed.). John Hennessy and David. Patterson. California:. Elsevier inc.
Jacob, B. and D. Wang, D. (2007). Memory Systems: Cache, DRAM, Disk. (2007). B. California:. Morgan Kaufmann Publishers Inc.
Jain, P. rachi and& Wadhawan, J. anakrani (2014). Desing and comparative analysis of SRAM cell structures using 0.5 nm technology. International Journal of Computer Applications, 87(3)..
Rainer Leupers, R. and& Olivier Temam, O. (2007). .Processor and system-on- chip simulation. (2007). USA. Springer.
Nathan, B. et al. (2011). The gem5 Simulator. (2011). Recuperado de http://research.cs.wisc.edu/multifacet/ papers/can11_gem5.pdfACM SIGARCH Computar Architecture News.

Wulf, M. (1995). cKee. Hitting the memory wall: implications of the obvious. (1995). USA. Computer Architecture News, 23, 20-24.